function cogEvalPreAndPll:
    useregset hub
    useregset cog
    inout I pll_saved_both
    body:
        let pll_saved_both (or32 pll_saved_both (and32 (lower32 (shr64 reg_cog_ctra_pllcounter (add32 (and32 (invert32 reg_cog_ctra_ctrplldiv) 0I7) 0I1c))) 0I1))
        switch reg_cog_ctra_ctrmode:
            case 0I0 0I4 0I8 0Ic 0I10 0I14 0I18 0I1c 0I1d 0I1e 0I1f:
            case 0I1 0I2 0I3 0I5 0I6 0I7 0I9 0Ia 0Ib 0Id 0Ie 0If 0I11 0I12 0I13 0I15 0I16 0I17 0I19 0I1a 0I1b:
                let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
        let pll_saved_both (or32 pll_saved_both (and32 (lower32 (shr64 reg_cog_ctrb_pllcounter (add32 (and32 (invert32 reg_cog_ctrb_ctrplldiv) 0I7) 0I1b))) 0I2))
        switch reg_cog_ctrb_ctrmode:
            case 0I0 0I4 0I8 0Ic 0I10 0I14 0I18 0I1c 0I1d 0I1e 0I1f:
            case 0I1 0I2 0I3 0I5 0I6 0I7 0I9 0Ia 0Ib 0Id 0Ie 0If 0I11 0I12 0I13 0I15 0I16 0I17 0I19 0I1a 0I1b:
                let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)

function macroCogPeripherals:
    useregset hub
    useregset cog
    local B posedge_snc1
    body:
        switch reg_cog_ctra_ctrmode:
            case 0I0 0I10:
            case 0I1 0I2 0I3 0I4 0I5 0I6 0I7 0I1f:
                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I8 0I9:
                if reg_cog_ctra_delayed0:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                let reg_cog_ctra_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctra_ctramask) 0I0)
            case 0Ia 0Ib:
                if (andB reg_cog_ctra_delayed0 (notB reg_cog_ctra_delayed1)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                let reg_cog_ctra_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctra_ctramask) 0I0)
            case 0Ic 0Id:
                if reg_cog_ctra_delayed0:
                    false:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                let reg_cog_ctra_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctra_ctramask) 0I0)
            case 0Ie 0If:
                if (andB (notB reg_cog_ctra_delayed0) reg_cog_ctra_delayed1):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                let reg_cog_ctra_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctra_ctramask) 0I0)
            case 0I11:
                if (andB (notB reg_cog_ctra_delayed1) (notB reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I12:
                if (andB (notB reg_cog_ctra_delayed1) reg_cog_ctra_delayed0):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I13:
                if reg_cog_ctra_delayed1:
                    false:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I14:
                if (andB reg_cog_ctra_delayed1 (notB reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I15:
                if reg_cog_ctra_delayed0:
                    false:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I16:
                if (neqB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I17:
                if (andB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0):
                    false:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I18:
                if (andB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I19:
                if (eqB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1a:
                if reg_cog_ctra_delayed0:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1b:
                if (orB reg_cog_ctra_delayed0 (notB reg_cog_ctra_delayed1)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1c:
                if reg_cog_ctra_delayed1:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1d:
                if (orB (notB reg_cog_ctra_delayed0) reg_cog_ctra_delayed1):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1e:
                if (orB reg_cog_ctra_delayed0 reg_cog_ctra_delayed1):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
        if (geq32 reg_cog_ctra_ctrmode 0I10):
            true:
                let reg_cog_ctra_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctra_ctramask) 0I0)
                let reg_cog_ctra_delayed1 (neq32 (and32 pin_in_wire reg_cog_ctra_ctrbmask) 0I0)
        switch reg_cog_ctrb_ctrmode:
            case 0I0 0I10:
            case 0I1 0I2 0I3 0I4 0I5 0I6 0I7 0I1f:
                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I8 0I9:
                if reg_cog_ctrb_delayed0:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                let reg_cog_ctrb_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctrb_ctramask) 0I0)
            case 0Ia 0Ib:
                if (andB reg_cog_ctrb_delayed0 (notB reg_cog_ctrb_delayed1)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                let reg_cog_ctrb_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctrb_ctramask) 0I0)
            case 0Ic 0Id:
                if reg_cog_ctrb_delayed0:
                    false:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                let reg_cog_ctrb_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctrb_ctramask) 0I0)
            case 0Ie 0If:
                if (andB (notB reg_cog_ctrb_delayed0) reg_cog_ctrb_delayed1):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                let reg_cog_ctrb_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctrb_ctramask) 0I0)
            case 0I11:
                if (andB (notB reg_cog_ctrb_delayed1) (notB reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I12:
                if (andB (notB reg_cog_ctrb_delayed1) reg_cog_ctrb_delayed0):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I13:
                if reg_cog_ctrb_delayed1:
                    false:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I14:
                if (andB reg_cog_ctrb_delayed1 (notB reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I15:
                if reg_cog_ctrb_delayed0:
                    false:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I16:
                if (neqB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I17:
                if (andB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0):
                    false:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I18:
                if (andB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I19:
                if (eqB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1a:
                if reg_cog_ctrb_delayed0:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1b:
                if (orB reg_cog_ctrb_delayed0 (notB reg_cog_ctrb_delayed1)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1c:
                if reg_cog_ctrb_delayed1:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1d:
                if (orB (notB reg_cog_ctrb_delayed0) reg_cog_ctrb_delayed1):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1e:
                if (orB reg_cog_ctrb_delayed0 reg_cog_ctrb_delayed1):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
        if (geq32 reg_cog_ctrb_ctrmode 0I10):
            true:
                let reg_cog_ctrb_delayed0 (neq32 (and32 pin_in_wire reg_cog_ctrb_ctramask) 0I0)
                let reg_cog_ctrb_delayed1 (neq32 (and32 pin_in_wire reg_cog_ctrb_ctrbmask) 0I0)
        if (neq32 reg_cog_vid_vcfg_vmode 0I0):
            true:
                let posedge_snc1 (andB (notB reg_cog_vid_snc1) reg_cog_vid_snc0)
                let reg_cog_vid_snc1 reg_cog_vid_snc0
                let reg_cog_vid_snc0 reg_cog_vid_capr
                if posedge_snc1:
                    true:
                        let reg_cog_vid_capr false

function cogEvalMain_async_vclk:
    useregset hub
    useregset cog
    local I loc_cog_vid_local_colormod
    body:
        if (neq32 (and32 reg_cog_vid_discrete 0I8) 0I0):
            true:
                if (neq32 (and32 (add32 (and32 (shr32 reg_cog_vid_discrete 0I4) 0If) reg_cog_vid_phase) 0I8) 0I0):
                    true:
                        let loc_cog_vid_local_colormod (add32 reg_cog_vid_discrete 0I7)
                        let reg_cog_vid_baseband (add32 0I8 (and32 (mux32 (testBit32 reg_cog_vid_vcfg_chroma 0I0) loc_cog_vid_local_colormod reg_cog_vid_discrete) 0I7))
                    false:
                        let loc_cog_vid_local_colormod (add32 reg_cog_vid_discrete 0I1)
                        let reg_cog_vid_baseband (add32 0I0 (and32 (mux32 (testBit32 reg_cog_vid_vcfg_chroma 0I0) loc_cog_vid_local_colormod reg_cog_vid_discrete) 0I7))
                let reg_cog_vid_composite (and32 (mux32 (testBit32 reg_cog_vid_vcfg_chroma 0I1) loc_cog_vid_local_colormod reg_cog_vid_discrete) 0I7)
            false:
                let reg_cog_vid_baseband (add32 0I0 (and32 (mux32 (testBit32 reg_cog_vid_vcfg_chroma 0I0) reg_cog_vid_discrete reg_cog_vid_discrete) 0I7))
                let reg_cog_vid_composite (and32 (mux32 (testBit32 reg_cog_vid_vcfg_chroma 0I1) reg_cog_vid_discrete reg_cog_vid_discrete) 0I7)
        if (eq32 reg_cog_vid_setr 0I1):
            true:
                let reg_cog_vid_cnt0 (and32 reg_cog_vid_vscl_pixelclocks 0Iff)
                let reg_cog_vid_setr (and32 reg_cog_vid_vscl_frameclocks 0Ifff)
                let reg_cog_vid_cnts (and32 reg_cog_vid_vscl_pixelclocks 0Iff)
                let reg_cog_vid_discrete (mux32 (andB (testBit32 reg_cog_vid_vcfg_chroma 0I2) (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I3)) (shr32 reg_cog_vid_saved_colors 0I18) (and32 (mux32 (andB (testBit32 reg_cog_vid_vcfg_chroma 0I2) (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I2)) (shr32 reg_cog_vid_saved_colors 0I10) (mux32 (testBit32 reg_cog_vid_saved_pixels 0I0) (shr32 reg_cog_vid_saved_colors 0I8) reg_cog_vid_saved_colors)) 0Iff))
                let reg_cog_vid_saved_pixels source
                let reg_cog_vid_saved_colors dest
                let reg_cog_vid_capr (muxB reg_cog_vid_snc1 false true)
            false:
                if (eq32 reg_cog_vid_cnt0 0I1):
                    true:
                        let reg_cog_vid_cnt0 (and32 reg_cog_vid_cnts 0Iff)
                        let reg_cog_vid_setr (and32 (sub32 reg_cog_vid_setr 0I1) 0Ifff)
                        let reg_cog_vid_discrete (mux32 (andB (testBit32 reg_cog_vid_vcfg_chroma 0I2) (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I3)) (shr32 reg_cog_vid_saved_colors 0I18) (and32 (mux32 (andB (testBit32 reg_cog_vid_vcfg_chroma 0I2) (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I2)) (shr32 reg_cog_vid_saved_colors 0I10) (mux32 (testBit32 reg_cog_vid_saved_pixels 0I0) (shr32 reg_cog_vid_saved_colors 0I8) reg_cog_vid_saved_colors)) 0Iff))
                        let reg_cog_vid_saved_pixels (mux32 (testBit32 reg_cog_vid_vcfg_chroma 0I2) (or32 (and32 reg_cog_vid_saved_pixels 0Ic0000000) (shr32 reg_cog_vid_saved_pixels 0I2)) (or32 (and32 reg_cog_vid_saved_pixels 0I80000000) (shr32 reg_cog_vid_saved_pixels 0I1)))
                    false:
                        let reg_cog_vid_cnt0 (and32 (sub32 reg_cog_vid_cnt0 0I1) 0Iff)
                        let reg_cog_vid_setr (and32 (sub32 reg_cog_vid_setr 0I1) 0Ifff)
                        let reg_cog_vid_discrete (mux32 (andB (testBit32 reg_cog_vid_vcfg_chroma 0I2) (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I3)) (shr32 reg_cog_vid_saved_colors 0I18) (and32 (mux32 (andB (testBit32 reg_cog_vid_vcfg_chroma 0I2) (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I2)) (shr32 reg_cog_vid_saved_colors 0I10) (mux32 (testBit32 reg_cog_vid_saved_pixels 0I0) (shr32 reg_cog_vid_saved_colors 0I8) reg_cog_vid_saved_colors)) 0Iff))
                if reg_cog_vid_snc1:
                    true:
                        let reg_cog_vid_capr false
        let reg_cog_vid_phase (and32 (add32 reg_cog_vid_phase 0I1) 0If)

function cogEvalMain_pinout:
    useregset hub
    useregset cog
    output I pin_out
    output I pin_dir
    local I outp_cog_ctra_pin_out
    local I outp_cog_ctrb_pin_out
    local I outp_cog_vid_pin_out
    body:
        let outp_cog_ctra_pin_out 0I0
        let outp_cog_ctrb_pin_out 0I0
        let outp_cog_vid_pin_out 0I0
        switch reg_cog_ctra_ctrmode:
            case 0I0 0I1 0I8 0Ia 0Ic 0Ie 0I10 0I11 0I12 0I13 0I14 0I15 0I16 0I17 0I18 0I19 0I1a 0I1b 0I1c 0I1d 0I1e 0I1f:
            case 0I2:
                if (testBit32 reg_pll_saved_both 0I1):
                    true:
                        let outp_cog_ctra_pin_out reg_cog_ctra_ctramask
            case 0I3:
                let outp_cog_ctra_pin_out (mux32 (testBit32 reg_pll_saved_both 0I1) reg_cog_ctra_ctramask reg_cog_ctra_ctrbmask)
            case 0I4:
                if (testBit64 reg_cog_ctra_phase 0I1f):
                    true:
                        let outp_cog_ctra_pin_out reg_cog_ctra_ctramask
            case 0I5:
                let outp_cog_ctra_pin_out (mux32 (testBit64 reg_cog_ctra_phase 0I1f) reg_cog_ctra_ctramask reg_cog_ctra_ctrbmask)
            case 0I6:
                if (testBit64 reg_cog_ctra_phase 0I20):
                    true:
                        let outp_cog_ctra_pin_out reg_cog_ctra_ctramask
            case 0I7:
                let outp_cog_ctra_pin_out (mux32 (testBit64 reg_cog_ctra_phase 0I20) reg_cog_ctra_ctramask reg_cog_ctra_ctrbmask)
            case 0I9 0Ib 0Id 0If:
                if reg_cog_ctra_delayed0:
                    false:
                        let outp_cog_ctra_pin_out reg_cog_ctra_ctrbmask
        switch reg_cog_ctrb_ctrmode:
            case 0I0 0I1 0I8 0Ia 0Ic 0Ie 0I10 0I11 0I12 0I13 0I14 0I15 0I16 0I17 0I18 0I19 0I1a 0I1b 0I1c 0I1d 0I1e 0I1f:
            case 0I2:
                if (testBit32 reg_pll_saved_both 0I2):
                    true:
                        let outp_cog_ctrb_pin_out reg_cog_ctrb_ctramask
            case 0I3:
                let outp_cog_ctrb_pin_out (mux32 (testBit32 reg_pll_saved_both 0I2) reg_cog_ctrb_ctramask reg_cog_ctrb_ctrbmask)
            case 0I4:
                if (testBit64 reg_cog_ctrb_phase 0I1f):
                    true:
                        let outp_cog_ctrb_pin_out reg_cog_ctrb_ctramask
            case 0I5:
                let outp_cog_ctrb_pin_out (mux32 (testBit64 reg_cog_ctrb_phase 0I1f) reg_cog_ctrb_ctramask reg_cog_ctrb_ctrbmask)
            case 0I6:
                if (testBit64 reg_cog_ctrb_phase 0I20):
                    true:
                        let outp_cog_ctrb_pin_out reg_cog_ctrb_ctramask
            case 0I7:
                let outp_cog_ctrb_pin_out (mux32 (testBit64 reg_cog_ctrb_phase 0I20) reg_cog_ctrb_ctramask reg_cog_ctrb_ctrbmask)
            case 0I9 0Ib 0Id 0If:
                if reg_cog_ctrb_delayed0:
                    false:
                        let outp_cog_ctrb_pin_out reg_cog_ctrb_ctrbmask
        switch reg_cog_vid_vcfg_vmode:
            case 0I3:
                let outp_cog_vid_pin_out (shl32 (and32 (mux32 (testBit32 reg_pll_saved_both 0I2) (add32 (add32 (shl32 reg_cog_vid_baseband 0I4) (mux32 (getPllOfCog reg_cog_vid_vcfg_auralsub) 0I0 0I8)) (sub32 0I7 (shr32 (add32 reg_cog_vid_composite 0I1) 0I1))) (add32 (add32 (shl32 reg_cog_vid_baseband 0I4) (mux32 (getPllOfCog reg_cog_vid_vcfg_auralsub) 0I8 0I0)) (and32 (shr32 reg_cog_vid_composite 0I1) 0I3))) reg_cog_vid_vcfg_vpins) reg_cog_vid_vcfg_vgroup)
            case 0I2:
                let outp_cog_vid_pin_out (shl32 (and32 (mux32 (testBit32 reg_pll_saved_both 0I2) (add32 (add32 reg_cog_vid_baseband (mux32 (getPllOfCog reg_cog_vid_vcfg_auralsub) 0I0 0I80)) (shl32 (sub32 0I7 (shr32 (add32 reg_cog_vid_composite 0I1) 0I1)) 0I4)) (add32 (add32 reg_cog_vid_baseband (mux32 (getPllOfCog reg_cog_vid_vcfg_auralsub) 0I80 0I0)) (shl32 (and32 (shr32 reg_cog_vid_composite 0I1) 0I3) 0I4))) reg_cog_vid_vcfg_vpins) reg_cog_vid_vcfg_vgroup)
            case 0I1:
                let outp_cog_vid_pin_out (shl32 (and32 reg_cog_vid_discrete reg_cog_vid_vcfg_vpins) reg_cog_vid_vcfg_vgroup)
            case 0I0:
        let pin_out (and32 (or32 (or32 (or32 outa outp_cog_ctra_pin_out) outp_cog_ctrb_pin_out) outp_cog_vid_pin_out) dira)
        let pin_dir dira
