//Diese Datei enthält die ungeänderte Ausgabe von dem propeller-clone-translator
regset hub:
    reg I sd
    reg I ad
    reg I sc
    reg I ac
    reg I dc
    reg I sys_q
    reg I cog_e
    reg I lock_e
    reg I lock_state
    reg I cfg_reg
    reg I cog_ena_reg
    reg I bus_q_reg
    reg I bus_sel_saved
    reg I enc
    reg I num
    reg I num_dcd
    reg I cog_start
    reg B rd
    reg B ed
    reg B rc
    reg B ec
    reg B wc
    reg B sys_c
    reg B sys
    reg I reg_hub_mem_q_reg
    regarray I reg_hub_mem_memory 0I4000
regset cog:
    reg I flags
    reg I dira
    reg I outa
    reg I instruction_reg
    reg I sy_reg
    reg I source
    reg I dest
    reg I p_reg
    reg I progctr
    reg I state
    reg B match
    reg B cancel
    reg B running
    reg B plla_saved
    reg B pllb_saved
    reg I reg_cog_vid_vcfg_vmode
    reg I reg_cog_vid_vcfg_auralsub
    reg I reg_cog_vid_vcfg_vgroup
    reg I reg_cog_vid_vcfg_vpins
    reg I reg_cog_vid_vscl_pixelclocks
    reg I reg_cog_vid_vscl_frameclocks
    reg I reg_cog_vid_composite
    reg I reg_cog_vid_baseband
    reg I reg_cog_vid_phase
    reg I reg_cog_vid_discrete
    reg I reg_cog_vid_saved_pixels
    reg I reg_cog_vid_saved_colors
    reg I reg_cog_vid_cnts
    reg I reg_cog_vid_cnt0
    reg I reg_cog_vid_setr
    reg B reg_cog_vid_vcfg_cmode
    reg B reg_cog_vid_vcfg_chroma1
    reg B reg_cog_vid_vcfg_chroma0
    reg B reg_cog_vid_capr
    reg B reg_cog_vid_snc0
    reg B reg_cog_vid_snc1
    reg I reg_cog_ctra_frequency
    reg L reg_cog_ctra_phase
    reg L reg_cog_ctra_pllcounter
    reg I reg_cog_ctra_ctrmode
    reg I reg_cog_ctra_ctrplldiv
    reg I reg_cog_ctra_ctrbpin
    reg I reg_cog_ctra_ctrapin
    reg B reg_cog_ctra_delayed0
    reg B reg_cog_ctra_delayed1
    reg B reg_cog_ctra_pll_saved
    reg I reg_cog_ctrb_frequency
    reg L reg_cog_ctrb_phase
    reg L reg_cog_ctrb_pllcounter
    reg I reg_cog_ctrb_ctrmode
    reg I reg_cog_ctrb_ctrplldiv
    reg I reg_cog_ctrb_ctrbpin
    reg I reg_cog_ctrb_ctrapin
    reg B reg_cog_ctrb_delayed0
    reg B reg_cog_ctrb_delayed1
    reg B reg_cog_ctrb_pll_saved
    reg I reg_cog_ram_q_reg
    regarray I reg_cog_ram_r 0I200
function cogPreEval:
    useregset cog
    output B pll_out
    local B outp_cog_ctra_pll
    local B outp_cog_ctrb_pll
    body:
        let reg_cog_ctra_pll_saved (eq32 (and32 (lower32 (shr64 reg_cog_ctra_pllcounter (add32 (and32 (invert32 reg_cog_ctra_ctrplldiv) 0I7) 0I1c))) 0I1) 0I1)
        let outp_cog_ctra_pll reg_cog_ctra_pll_saved
        let reg_cog_ctrb_pll_saved (eq32 (and32 (lower32 (shr64 reg_cog_ctrb_pllcounter (add32 (and32 (invert32 reg_cog_ctrb_ctrplldiv) 0I7) 0I1c))) 0I1) 0I1)
        let outp_cog_ctrb_pll reg_cog_ctrb_pll_saved
        let plla_saved outp_cog_ctra_pll
        let pllb_saved outp_cog_ctrb_pll
        let pll_out plla_saved
function cogEvalMain:
    useregset hub
    useregset cog
    input B nres
    input B ena_bus
    input B ptr_w
    input I ptr_d
    input B ena
    input B bus_sel
    input I bus_q
    input B bus_c
    input B bus_ack
    input I cnt
    input I pll_in
    input I pin_in
    input B posedge_clk_cog
    input B negedge_nres
    input B negedge_ena
    input B posedge_clk_pll
    input B posedge_vclk
    input B posedge_snc1
    output B bus_r
    output B bus_e
    output B bus_w
    output I bus_s
    output I bus_a
    output I bus_d
    output I pin_out
    output I pin_dir
    local I sx
    local I px
    local I i
    local I instr_src
    local I instr_dst
    local I instr_opcode
    local B jump
    local B cond
    local B jump_cancel
    local B wio
    local B match_prev
    local I in_cog_alu_i
    local I in_cog_alu_s
    local I in_cog_alu_d
    local I in_cog_alu_p
    local B in_cog_alu_run
    local B in_cog_alu_ci
    local B in_cog_alu_zi
    local I in_cog_alu_bus_q
    local B in_cog_alu_bus_c
    local L loc_cog_alu_tmpResSigned
    local L loc_cog_alu_tmpResUnsigned
    local I loc_cog_alu_tmpResBitOp
    local B outp_cog_alu_wr
    local I outp_cog_alu_r
    local B outp_cog_alu_co
    local B outp_cog_alu_zo
    local B in_cog_ctra_ena
    local B in_cog_ctra_setctr
    local B in_cog_ctra_setfrq
    local B in_cog_ctra_setphs
    local I in_cog_ctra_data
    local I in_cog_ctra_pin_in
    local B in_cog_ctra_posedge_clk_cog
    local B in_cog_ctra_posedge_clk_pll
    local B in_cog_ctra_negedge_ena
    local L outp_cog_ctra_phs
    local I outp_cog_ctra_pin_out
    local B in_cog_ctrb_ena
    local B in_cog_ctrb_setctr
    local B in_cog_ctrb_setfrq
    local B in_cog_ctrb_setphs
    local I in_cog_ctrb_data
    local I in_cog_ctrb_pin_in
    local B in_cog_ctrb_posedge_clk_cog
    local B in_cog_ctrb_posedge_clk_pll
    local B in_cog_ctrb_negedge_ena
    local L outp_cog_ctrb_phs
    local I outp_cog_ctrb_pin_out
    local B in_cog_vid_ena
    local B in_cog_vid_setvid
    local B in_cog_vid_setscl
    local I in_cog_vid_data
    local I in_cog_vid_pixel
    local I in_cog_vid_color
    local I in_cog_vid_aural
    local B in_cog_vid_carrier
    local B in_cog_vid_posedge_clk_cog
    local B in_cog_vid_negedge_ena
    local B in_cog_vid_posedge_vclk
    local B in_cog_vid_posedge_snc1
    local I loc_cog_vid_local_colormod
    local B loc_cog_vid_local_enable
    local B loc_cog_vid_local_new_set
    local B loc_cog_vid_local_new_cnt
    local B loc_cog_vid_local_capr_next
    local B loc_cog_vid_local_colorphs
    local B outp_cog_vid_ack
    local I outp_cog_vid_pin_out
    local B in_cog_ram_posedge_clk_cog
    local B in_cog_ram_ena
    local B in_cog_ram_w
    local I in_cog_ram_d
    local I in_cog_ram_a
    local I outp_cog_ram_q
    body:
        let i (mux32 running instruction_reg (or32 0I8840000 (shl32 p_reg 0I9)))
        let instr_opcode (and32 (shr32 i 0I1a) 0I3f)
        let bus_r false
        let bus_e false
        let bus_w false
        let bus_s 0I0
        let bus_a 0I0
        let bus_d 0I0
        if bus_sel:
            true:
                let bus_r running
                let bus_e (andB (eq32 state 0I5) (eq32 (and32 instr_opcode 0I3c) 0I0))
                let bus_w (notB (testBit32 i 0I17))
                let bus_s (and32 instr_opcode 0I3)
                let bus_a (mux32 running (and32 source 0Iffff) (or32 (and32 (shl32 (add32 (and32 progctr 0Ifffff) p_reg) 0I2) 0Iffff) (and32 source 0I3)))
                let bus_d dest
        let instr_dst (and32 (shr32 i 0I9) 0I1ff)
        let instr_src (and32 i 0I1ff)
        let in_cog_alu_i instr_opcode
        let in_cog_alu_s source
        let in_cog_alu_d dest
        let in_cog_alu_p p_reg
        let in_cog_alu_run running
        let in_cog_alu_ci (testBit32 flags 0I1)
        let in_cog_alu_zi (testBit32 flags 0I0)
        let in_cog_alu_bus_q bus_q
        let in_cog_alu_bus_c bus_c
        let outp_cog_alu_wr true
        let outp_cog_alu_zo false
        let outp_cog_alu_co false
        let outp_cog_alu_r 0I0
        let loc_cog_alu_tmpResSigned 0L0
        let loc_cog_alu_tmpResUnsigned 0L0
        let loc_cog_alu_tmpResBitOp 0I0
        switch in_cog_alu_i:
            case 0I0 0I1 0I2 0I3 0I4 0I5 0I6 0I7:
                let outp_cog_alu_co in_cog_alu_bus_c
                if (orB in_cog_alu_run (neq32 (and32 in_cog_alu_p 0I1f0) 0I1f0)):
                    true:
                        let outp_cog_alu_r in_cog_alu_bus_q
                        let outp_cog_alu_zo (eq32 outp_cog_alu_r 0I0)
                    false:
                        let outp_cog_alu_r 0I0
                        let outp_cog_alu_zo true
            case 0I8:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I0)
                let loc_cog_alu_tmpResBitOp (orWithZFlag (shr32 in_cog_alu_d (and32 in_cog_alu_s 0I1f)) (shl32 in_cog_alu_d (sub32 0I20 (and32 in_cog_alu_s 0I1f))))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0I9:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I1f)
                let loc_cog_alu_tmpResBitOp (orWithZFlag (shl32 in_cog_alu_d (and32 in_cog_alu_s 0I1f)) (shr32 in_cog_alu_d (sub32 0I20 (and32 in_cog_alu_s 0I1f))))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0Ia:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I0)
                let loc_cog_alu_tmpResBitOp (shrWithZFlag in_cog_alu_d (and32 in_cog_alu_s 0I1f))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0Ib:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I1f)
                let loc_cog_alu_tmpResBitOp (shlWithZFlag in_cog_alu_d (and32 in_cog_alu_s 0I1f))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0Ic:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I0)
                if in_cog_alu_ci:
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag (shr32 in_cog_alu_d (and32 in_cog_alu_s 0I1f)) (shl32 0Iffffffff (sub32 0I20 (and32 in_cog_alu_s 0I1f))))
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (shrWithZFlag in_cog_alu_d (and32 in_cog_alu_s 0I1f))
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0Id:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I1f)
                if in_cog_alu_ci:
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag (shl32 in_cog_alu_d (and32 in_cog_alu_s 0I1f)) (shr32 0Iffffffff (sub32 0I20 (and32 in_cog_alu_s 0I1f))))
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (shlWithZFlag in_cog_alu_d (and32 in_cog_alu_s 0I1f))
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0Ie:
                let outp_cog_alu_co (testBit32 in_cog_alu_d 0I0)
                if (testBit32 in_cog_alu_d 0I1f):
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag (shr32 in_cog_alu_d (and32 in_cog_alu_s 0I1f)) (shl32 0Iffffffff (sub32 0I20 (and32 in_cog_alu_s 0I1f))))
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (shrWithZFlag in_cog_alu_d (and32 in_cog_alu_s 0I1f))
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0If:
                let outp_cog_alu_r (or32 (shr32 (and32 in_cog_alu_d 0Iaaaaaaaa) 0I1) (shl32 (and32 in_cog_alu_d 0I55555555) 0I1))
                let outp_cog_alu_r (or32 (shr32 (and32 outp_cog_alu_r 0Icccccccc) 0I2) (shl32 (and32 outp_cog_alu_r 0I33333333) 0I2))
                let outp_cog_alu_r (or32 (shr32 (and32 outp_cog_alu_r 0If0f0f0f0) 0I4) (shl32 (and32 outp_cog_alu_r 0If0f0f0f) 0I4))
                let outp_cog_alu_r (or32 (shr32 (and32 outp_cog_alu_r 0Iff00ff00) 0I8) (shl32 (and32 outp_cog_alu_r 0Iff00ff) 0I8))
                let outp_cog_alu_r (or32 (shr32 outp_cog_alu_r 0I10) (shl32 outp_cog_alu_r 0I10))
                let outp_cog_alu_r (shr32 outp_cog_alu_r (and32 in_cog_alu_s 0I1f))
                let outp_cog_alu_zo (eq32 outp_cog_alu_r 0I0)
                let outp_cog_alu_co (eq32 (and32 in_cog_alu_d 0I1) 0I1)
            case 0I10:
                let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
                let outp_cog_alu_r in_cog_alu_s
                let outp_cog_alu_co (sgnle32 in_cog_alu_d in_cog_alu_s)
                let outp_cog_alu_wr outp_cog_alu_co
            case 0I11:
                let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
                let outp_cog_alu_r in_cog_alu_s
                let outp_cog_alu_co (sgnle32 in_cog_alu_d in_cog_alu_s)
                let outp_cog_alu_wr (notB outp_cog_alu_co)
            case 0I12:
                let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
                let outp_cog_alu_r in_cog_alu_s
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s true false)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_wr outp_cog_alu_co
            case 0I13:
                let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
                let outp_cog_alu_r in_cog_alu_s
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s true false)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_wr (notB outp_cog_alu_co)
            case 0I14:
                let outp_cog_alu_co (le32 in_cog_alu_d in_cog_alu_s)
                let loc_cog_alu_tmpResBitOp (orWithZFlag (and32 in_cog_alu_d 0Ifffffe00) (and32 in_cog_alu_s 0I1ff))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0I15:
                let outp_cog_alu_co (le32 in_cog_alu_d in_cog_alu_s)
                let loc_cog_alu_tmpResBitOp (orWithZFlag (and32 in_cog_alu_d 0Ifffc01ff) (shl32 (and32 in_cog_alu_s 0I1ff) 0I9))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0I16:
                let outp_cog_alu_co (le32 in_cog_alu_d in_cog_alu_s)
                let loc_cog_alu_tmpResBitOp (orWithZFlag (and32 in_cog_alu_d 0I7fffff) (shl32 (and32 in_cog_alu_s 0I1ff) 0I17))
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0I17:
                let outp_cog_alu_co (le32 in_cog_alu_d in_cog_alu_s)
                let loc_cog_alu_tmpResBitOp (orWithZFlag (and32 in_cog_alu_d 0Ifffffe00) in_cog_alu_p)
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0I18:
                let loc_cog_alu_tmpResBitOp (andWithZFlag in_cog_alu_s in_cog_alu_d)
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I19:
                let loc_cog_alu_tmpResBitOp (andWithZFlag (invert32 in_cog_alu_s) in_cog_alu_d)
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I1a:
                let loc_cog_alu_tmpResBitOp (orWithZFlag in_cog_alu_s in_cog_alu_d)
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I1b:
                let loc_cog_alu_tmpResBitOp (xorWithZFlag in_cog_alu_s in_cog_alu_d)
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I1c:
                if in_cog_alu_ci:
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag in_cog_alu_s in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (andWithZFlag (invert32 in_cog_alu_s) in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I1d:
                if (notB in_cog_alu_ci):
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag in_cog_alu_s in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (andWithZFlag (invert32 in_cog_alu_s) in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I1e:
                if in_cog_alu_zi:
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag in_cog_alu_s in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (andWithZFlag (invert32 in_cog_alu_s) in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I1f:
                if (notB in_cog_alu_zi):
                    true:
                        let loc_cog_alu_tmpResBitOp (orWithZFlag in_cog_alu_s in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let loc_cog_alu_tmpResBitOp (andWithZFlag (invert32 in_cog_alu_s) in_cog_alu_d)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_co (getParity outp_cog_alu_r)
            case 0I20:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s false false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I21:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s true false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I22:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s (testBit32 in_cog_alu_s 0I1f) false)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I23:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s (notB (testBit32 in_cog_alu_s 0I1f)) false)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I24:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s in_cog_alu_ci false)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I25:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s (notB in_cog_alu_ci) false)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I26:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s in_cog_alu_zi false)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I27:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s (notB in_cog_alu_zi) false)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I28:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
                let outp_cog_alu_r in_cog_alu_s
            case 0I29:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
            case 0I2a:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                if outp_cog_alu_co:
                    true:
                        let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let outp_cog_alu_r in_cog_alu_s
                        let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
            case 0I2b:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                if (notB outp_cog_alu_co):
                    true:
                        let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let outp_cog_alu_r in_cog_alu_s
                        let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
            case 0I2c:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                if in_cog_alu_ci:
                    true:
                        let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let outp_cog_alu_r in_cog_alu_s
                        let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
            case 0I2d:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                if (notB in_cog_alu_ci):
                    true:
                        let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let outp_cog_alu_r in_cog_alu_s
                        let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
            case 0I2e:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                if in_cog_alu_zi:
                    true:
                        let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let outp_cog_alu_r in_cog_alu_s
                        let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
            case 0I2f:
                let outp_cog_alu_co (testBit32 in_cog_alu_s 0I1f)
                if (notB in_cog_alu_zi):
                    true:
                        let loc_cog_alu_tmpResBitOp (negWithZFlag in_cog_alu_s)
                        let outp_cog_alu_r (getBitOpResult loc_cog_alu_tmpResBitOp)
                        let outp_cog_alu_zo (getBitOpZero loc_cog_alu_tmpResBitOp)
                    false:
                        let outp_cog_alu_r in_cog_alu_s
                        let outp_cog_alu_zo (eq32 in_cog_alu_s 0I0)
            case 0I30:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s true false)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (neqB (eq32 (and32 (shr32 outp_cog_alu_r 0I1f) 0I1) 0I1) (getSignedCarry loc_cog_alu_tmpResSigned))
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I31:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s true in_cog_alu_ci)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (neqB (eq32 (and32 (shr32 outp_cog_alu_r 0I1f) 0I1) 0I1) (getSignedCarry loc_cog_alu_tmpResSigned))
                let outp_cog_alu_zo (andB in_cog_alu_zi (getSignedZero loc_cog_alu_tmpResSigned))
            case 0I32:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s false in_cog_alu_ci)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (andB in_cog_alu_zi (getUnsignedZero loc_cog_alu_tmpResUnsigned))
            case 0I33:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s true in_cog_alu_ci)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (andB in_cog_alu_zi (getUnsignedZero loc_cog_alu_tmpResUnsigned))
            case 0I34:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s false false)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I35:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s true false)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (getSignedZero loc_cog_alu_tmpResSigned)
            case 0I36:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s false in_cog_alu_ci)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (andB in_cog_alu_zi (getSignedZero loc_cog_alu_tmpResSigned))
            case 0I37:
                let loc_cog_alu_tmpResSigned (signedAddOrSub in_cog_alu_d in_cog_alu_s true in_cog_alu_ci)
                let outp_cog_alu_r (getSignedResult loc_cog_alu_tmpResSigned)
                let outp_cog_alu_co (getSignedCarry loc_cog_alu_tmpResSigned)
                let outp_cog_alu_zo (andB in_cog_alu_zi (getSignedZero loc_cog_alu_tmpResSigned))
            case 0I38:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s true false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (notB (getUnsignedCarry loc_cog_alu_tmpResUnsigned))
                let outp_cog_alu_wr outp_cog_alu_co
            case 0I39:
                let outp_cog_alu_co (eq32 in_cog_alu_d 0I0)
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d 0I1 true false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I3a:
                let outp_cog_alu_zo (eq32 in_cog_alu_d 0I0)
                let outp_cog_alu_r in_cog_alu_d
                let outp_cog_alu_co false
            case 0I3b:
                let outp_cog_alu_zo (eq32 in_cog_alu_d 0I0)
                let outp_cog_alu_r in_cog_alu_d
                let outp_cog_alu_co false
            case 0I3c:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s false false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I3d:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s false true)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I3e:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s false false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
            case 0I3f:
                let loc_cog_alu_tmpResUnsigned (unsignedAddOrSub in_cog_alu_d in_cog_alu_s false false)
                let outp_cog_alu_r (getUnsignedResult loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_co (getUnsignedCarry loc_cog_alu_tmpResUnsigned)
                let outp_cog_alu_zo (getUnsignedZero loc_cog_alu_tmpResUnsigned)
        let cond (andB (notB cancel) (eq32 (and32 (shr32 (and32 (shr32 i 0I12) 0If) flags) 0I1) 0I1))
        if (orB (eq32 state 0I3) (eq32 state 0I4)):
            true:
                let jump true
                if (eq32 instr_opcode 0I17):
                    true:
                        let jump_cancel false
                    false:
                        if (eq32 instr_opcode 0I39):
                            true:
                                let jump_cancel (eq32 dest 0I1)
                            false:
                                if (eq32 instr_opcode 0I3a):
                                    true:
                                        let jump_cancel (eq32 dest 0I0)
                                    false:
                                        if (eq32 instr_opcode 0I3b):
                                            true:
                                                let jump_cancel (neq32 dest 0I0)
                                            false:
                                                let jump false
                let wio (andB (andB (eq32 state 0I4) cond) (testBit32 i 0I17))
        let in_cog_ctra_ena ena
        let in_cog_ctra_setctr (andB wio (eq32 instr_dst 0I1f8))
        let in_cog_ctra_setfrq (andB wio (eq32 instr_dst 0I1fa))
        let in_cog_ctra_setphs (andB wio (eq32 instr_dst 0I1fc))
        let in_cog_ctra_data outp_cog_alu_r
        let in_cog_ctra_pin_in pin_in
        let in_cog_ctra_posedge_clk_cog posedge_clk_cog
        let in_cog_ctra_posedge_clk_pll posedge_clk_pll
        let in_cog_ctra_negedge_ena negedge_ena
        let outp_cog_ctra_phs reg_cog_ctra_phase
        let outp_cog_ctra_pin_out 0I0
        switch reg_cog_ctra_ctrmode:
            case 0I0:
            case 0I1:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I2:
                if reg_cog_ctra_pll_saved:
                    true:
                        let outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrapin)
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I3:
                let outp_cog_ctra_pin_out (shl32 0I1 (mux32 reg_cog_ctra_pll_saved reg_cog_ctra_ctrapin reg_cog_ctra_ctrbpin))
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I4:
                if (testBit64 reg_cog_ctra_phase 0I1f):
                    true:
                        let outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrapin)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I5:
                let outp_cog_ctra_pin_out (shl32 0I1 (mux32 (testBit64 reg_cog_ctra_phase 0I1f) reg_cog_ctra_ctrapin reg_cog_ctra_ctrbpin))
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I6:
                if (testBit64 reg_cog_ctra_phase 0I20):
                    true:
                        let outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrapin)
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I7:
                let outp_cog_ctra_pin_out (shl32 0I1 (mux32 (testBit64 reg_cog_ctra_phase 0I20) reg_cog_ctra_ctrapin reg_cog_ctra_ctrbpin))
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I8:
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if reg_cog_ctra_delayed0:
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0I9:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctra_delayed0):
                    true:
                        let outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrbpin)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if reg_cog_ctra_delayed0:
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0Ia:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if (andB reg_cog_ctra_delayed0 (notB reg_cog_ctra_delayed1)):
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0Ib:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctra_delayed0):
                    true:
                        let outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrbpin)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if (andB reg_cog_ctra_delayed0 (notB reg_cog_ctra_delayed1)):
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0Ic:
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if (notB reg_cog_ctra_delayed0):
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0Id:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctra_delayed0):
                    true:
                        let outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrbpin)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if (notB reg_cog_ctra_delayed0):
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0Ie:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if (andB (notB reg_cog_ctra_delayed0) reg_cog_ctra_delayed1):
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0If:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctra_delayed0):
                    true:
                        let outp_cog_ctra_pin_out (or32 outp_cog_ctra_pin_out (shl32 0I1 reg_cog_ctra_ctrbpin))
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        if (andB (notB reg_cog_ctra_delayed0) reg_cog_ctra_delayed1):
                            true:
                                let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
                        let reg_cog_ctra_delayed1 reg_cog_ctra_delayed0
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
            case 0I10:
            case 0I11:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (andB (notB reg_cog_ctra_delayed1) (notB reg_cog_ctra_delayed0))):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I12:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (andB (notB reg_cog_ctra_delayed1) reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I13:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (notB reg_cog_ctra_delayed1)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I14:
                if (andB in_cog_ctra_posedge_clk_cog (andB reg_cog_ctra_delayed1 (notB reg_cog_ctra_delayed0))):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I15:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (notB reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I16:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (neqB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I17:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (notB (andB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0))):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I18:
                if (andB in_cog_ctra_posedge_clk_cog (andB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I19:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (eqB reg_cog_ctra_delayed1 reg_cog_ctra_delayed0)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1a:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog reg_cog_ctra_delayed0):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1b:
                if in_cog_ctra_posedge_clk_pll:
                    true:
                        let reg_cog_ctra_pllcounter (and64 (add64 reg_cog_ctra_pllcounter (cast64 reg_cog_ctra_frequency)) 0Lfffffffff)
                if (andB in_cog_ctra_posedge_clk_cog (orB reg_cog_ctra_delayed0 (notB reg_cog_ctra_delayed1))):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1c:
                if (andB in_cog_ctra_posedge_clk_cog reg_cog_ctra_delayed1):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1d:
                if (andB in_cog_ctra_posedge_clk_cog (orB (notB reg_cog_ctra_delayed0) reg_cog_ctra_delayed1)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1e:
                if (andB in_cog_ctra_posedge_clk_cog (orB reg_cog_ctra_delayed0 reg_cog_ctra_delayed1)):
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
            case 0I1f:
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_phase (add64 (and64 reg_cog_ctra_phase 0Lffffffff) (cast64 reg_cog_ctra_frequency))
        if (geq32 reg_cog_ctra_ctrmode 0I10):
            true:
                if in_cog_ctra_posedge_clk_cog:
                    true:
                        let reg_cog_ctra_delayed0 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrapin) 0I1) 0I1)
                        let reg_cog_ctra_delayed1 (eq32 (and32 (shr32 in_cog_ctra_pin_in reg_cog_ctra_ctrbpin) 0I1) 0I1)
        if in_cog_ctra_posedge_clk_cog:
            true:
                if in_cog_ctra_setphs:
                    true:
                        let reg_cog_ctra_phase (cast64 in_cog_ctra_data)
                if in_cog_ctra_setfrq:
                    true:
                        let reg_cog_ctra_frequency in_cog_ctra_data
        if (orB in_cog_ctra_posedge_clk_cog in_cog_ctra_negedge_ena):
            true:
                if (notB in_cog_ctra_ena):
                    true:
                        let reg_cog_ctra_ctrmode 0I0
                        let reg_cog_ctra_ctrplldiv 0I0
                        let reg_cog_ctra_ctrbpin 0I0
                        let reg_cog_ctra_ctrapin 0I0
                    false:
                        if in_cog_ctra_setctr:
                            true:
                                let reg_cog_ctra_ctrmode (and32 (shr32 in_cog_ctra_data 0I1a) 0I3f)
                                let reg_cog_ctra_ctrplldiv (and32 (shr32 in_cog_ctra_data 0I17) 0I7)
                                let reg_cog_ctra_ctrbpin (and32 (shr32 in_cog_ctra_data 0I9) 0I1f)
                                let reg_cog_ctra_ctrapin (and32 in_cog_ctra_data 0I1f)
        let in_cog_ctrb_ena ena
        let in_cog_ctrb_setctr (andB wio (eq32 instr_dst 0I1f9))
        let in_cog_ctrb_setfrq (andB wio (eq32 instr_dst 0I1fb))
        let in_cog_ctrb_setphs (andB wio (eq32 instr_dst 0I1fd))
        let in_cog_ctrb_data outp_cog_alu_r
        let in_cog_ctrb_pin_in pin_in
        let in_cog_ctrb_posedge_clk_cog posedge_clk_cog
        let in_cog_ctrb_posedge_clk_pll posedge_clk_pll
        let in_cog_ctrb_negedge_ena negedge_ena
        let outp_cog_ctrb_phs reg_cog_ctrb_phase
        let outp_cog_ctrb_pin_out 0I0
        switch reg_cog_ctrb_ctrmode:
            case 0I0:
            case 0I1:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I2:
                if reg_cog_ctrb_pll_saved:
                    true:
                        let outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrapin)
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I3:
                let outp_cog_ctrb_pin_out (shl32 0I1 (mux32 reg_cog_ctrb_pll_saved reg_cog_ctrb_ctrapin reg_cog_ctrb_ctrbpin))
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I4:
                if (testBit64 reg_cog_ctrb_phase 0I1f):
                    true:
                        let outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrapin)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I5:
                let outp_cog_ctrb_pin_out (shl32 0I1 (mux32 (testBit64 reg_cog_ctrb_phase 0I1f) reg_cog_ctrb_ctrapin reg_cog_ctrb_ctrbpin))
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I6:
                if (testBit64 reg_cog_ctrb_phase 0I20):
                    true:
                        let outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrapin)
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I7:
                let outp_cog_ctrb_pin_out (shl32 0I1 (mux32 (testBit64 reg_cog_ctrb_phase 0I20) reg_cog_ctrb_ctrapin reg_cog_ctrb_ctrbpin))
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I8:
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if reg_cog_ctrb_delayed0:
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0I9:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctrb_delayed0):
                    true:
                        let outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrbpin)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if reg_cog_ctrb_delayed0:
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0Ia:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if (andB reg_cog_ctrb_delayed0 (notB reg_cog_ctrb_delayed1)):
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0Ib:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctrb_delayed0):
                    true:
                        let outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrbpin)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if (andB reg_cog_ctrb_delayed0 (notB reg_cog_ctrb_delayed1)):
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0Ic:
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if (notB reg_cog_ctrb_delayed0):
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0Id:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctrb_delayed0):
                    true:
                        let outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrbpin)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if (notB reg_cog_ctrb_delayed0):
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0Ie:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if (andB (notB reg_cog_ctrb_delayed0) reg_cog_ctrb_delayed1):
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0If:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (notB reg_cog_ctrb_delayed0):
                    true:
                        let outp_cog_ctrb_pin_out (or32 outp_cog_ctrb_pin_out (shl32 0I1 reg_cog_ctrb_ctrbpin))
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        if (andB (notB reg_cog_ctrb_delayed0) reg_cog_ctrb_delayed1):
                            true:
                                let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
                        let reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
            case 0I10:
            case 0I11:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (andB (notB reg_cog_ctrb_delayed1) (notB reg_cog_ctrb_delayed0))):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I12:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (andB (notB reg_cog_ctrb_delayed1) reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I13:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (notB reg_cog_ctrb_delayed1)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I14:
                if (andB in_cog_ctrb_posedge_clk_cog (andB reg_cog_ctrb_delayed1 (notB reg_cog_ctrb_delayed0))):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I15:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (notB reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I16:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (neqB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I17:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (notB (andB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0))):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I18:
                if (andB in_cog_ctrb_posedge_clk_cog (andB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I19:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (eqB reg_cog_ctrb_delayed1 reg_cog_ctrb_delayed0)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1a:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog reg_cog_ctrb_delayed0):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1b:
                if in_cog_ctrb_posedge_clk_pll:
                    true:
                        let reg_cog_ctrb_pllcounter (and64 (add64 reg_cog_ctrb_pllcounter (cast64 reg_cog_ctrb_frequency)) 0Lfffffffff)
                if (andB in_cog_ctrb_posedge_clk_cog (orB reg_cog_ctrb_delayed0 (notB reg_cog_ctrb_delayed1))):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1c:
                if (andB in_cog_ctrb_posedge_clk_cog reg_cog_ctrb_delayed1):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1d:
                if (andB in_cog_ctrb_posedge_clk_cog (orB (notB reg_cog_ctrb_delayed0) reg_cog_ctrb_delayed1)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1e:
                if (andB in_cog_ctrb_posedge_clk_cog (orB reg_cog_ctrb_delayed0 reg_cog_ctrb_delayed1)):
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
            case 0I1f:
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_phase (add64 (and64 reg_cog_ctrb_phase 0Lffffffff) (cast64 reg_cog_ctrb_frequency))
        if (geq32 reg_cog_ctrb_ctrmode 0I10):
            true:
                if in_cog_ctrb_posedge_clk_cog:
                    true:
                        let reg_cog_ctrb_delayed0 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrapin) 0I1) 0I1)
                        let reg_cog_ctrb_delayed1 (eq32 (and32 (shr32 in_cog_ctrb_pin_in reg_cog_ctrb_ctrbpin) 0I1) 0I1)
        if in_cog_ctrb_posedge_clk_cog:
            true:
                if in_cog_ctrb_setphs:
                    true:
                        let reg_cog_ctrb_phase (cast64 in_cog_ctrb_data)
                if in_cog_ctrb_setfrq:
                    true:
                        let reg_cog_ctrb_frequency in_cog_ctrb_data
        if (orB in_cog_ctrb_posedge_clk_cog in_cog_ctrb_negedge_ena):
            true:
                if (notB in_cog_ctrb_ena):
                    true:
                        let reg_cog_ctrb_ctrmode 0I0
                        let reg_cog_ctrb_ctrplldiv 0I0
                        let reg_cog_ctrb_ctrbpin 0I0
                        let reg_cog_ctrb_ctrapin 0I0
                    false:
                        if in_cog_ctrb_setctr:
                            true:
                                let reg_cog_ctrb_ctrmode (and32 (shr32 in_cog_ctrb_data 0I1a) 0I3f)
                                let reg_cog_ctrb_ctrplldiv (and32 (shr32 in_cog_ctrb_data 0I17) 0I7)
                                let reg_cog_ctrb_ctrbpin (and32 (shr32 in_cog_ctrb_data 0I9) 0I1f)
                                let reg_cog_ctrb_ctrapin (and32 in_cog_ctrb_data 0I1f)
        if (orB (eq32 state 0I3) (eq32 state 0I4)):
            true:
                let sx (mux32 (testBit32 i 0I16) instr_src (mux32 (le32 instr_src 0I1f0) sy_reg (mux32 (eq32 instr_src 0I1f0) (and32 (shr32 progctr 0Ic) 0Ifffc) (mux32 (eq32 instr_src 0I1f1) cnt (mux32 (eq32 instr_src 0I1f2) pin_in (mux32 (eq32 instr_src 0I1fc) (lower32 outp_cog_ctra_phs) (mux32 (eq32 instr_src 0I1fd) (lower32 outp_cog_ctrb_phs) sy_reg)))))))
                let px (and32 (mux32 (andB cond jump) sx p_reg) 0I1ff)
        let in_cog_vid_ena ena
        let in_cog_vid_setvid (andB wio (eq32 instr_dst 0I1fe))
        let in_cog_vid_setscl (andB wio (eq32 instr_dst 0I1ff))
        let in_cog_vid_data outp_cog_alu_r
        let in_cog_vid_pixel source
        let in_cog_vid_color dest
        let in_cog_vid_aural pll_in
        let in_cog_vid_carrier pllb_saved
        let in_cog_vid_posedge_clk_cog posedge_clk_cog
        let in_cog_vid_negedge_ena negedge_ena
        let in_cog_vid_posedge_vclk posedge_vclk
        let in_cog_vid_posedge_snc1 posedge_snc1
        let loc_cog_vid_local_enable (neq32 reg_cog_vid_vcfg_vmode 0I0)
        let loc_cog_vid_local_capr_next reg_cog_vid_capr
        let outp_cog_vid_ack reg_cog_vid_snc0
        let outp_cog_vid_pin_out 0I0
        switch reg_cog_vid_vcfg_vmode:
            case 0I3:
                let outp_cog_vid_pin_out (shl32 (and32 (add32 (add32 (shl32 reg_cog_vid_baseband 0I4) (mux32 (neqB in_cog_vid_carrier (testBit32 in_cog_vid_aural reg_cog_vid_vcfg_auralsub)) 0I8 0I0)) (mux32 in_cog_vid_carrier (sub32 0I7 (shr32 (add32 reg_cog_vid_composite 0I1) 0I1)) (and32 (shr32 reg_cog_vid_composite 0I1) 0I3))) reg_cog_vid_vcfg_vpins) reg_cog_vid_vcfg_vgroup)
            case 0I2:
                let outp_cog_vid_pin_out (shl32 (and32 (add32 (add32 reg_cog_vid_baseband (mux32 (neqB in_cog_vid_carrier (testBit32 in_cog_vid_aural reg_cog_vid_vcfg_auralsub)) 0I80 0I0)) (shl32 (mux32 in_cog_vid_carrier (sub32 0I7 (shr32 (add32 reg_cog_vid_composite 0I1) 0I1)) (and32 (shr32 reg_cog_vid_composite 0I1) 0I3)) 0I4)) reg_cog_vid_vcfg_vpins) reg_cog_vid_vcfg_vgroup)
            case 0I1:
                let outp_cog_vid_pin_out (shl32 (and32 reg_cog_vid_discrete reg_cog_vid_vcfg_vpins) reg_cog_vid_vcfg_vgroup)
            case 0I0:
                let outp_cog_vid_pin_out 0I0
        if (orB in_cog_vid_posedge_vclk in_cog_vid_posedge_snc1):
            true:
                let loc_cog_vid_local_new_set (eq32 reg_cog_vid_setr 0I1)
                let loc_cog_vid_local_new_cnt (eq32 reg_cog_vid_cnt0 0I1)
                if reg_cog_vid_snc1:
                    true:
                        let loc_cog_vid_local_capr_next false
                    false:
                        if loc_cog_vid_local_new_set:
                            true:
                                let loc_cog_vid_local_capr_next true
                if in_cog_vid_posedge_vclk:
                    true:
                        let loc_cog_vid_local_colorphs false
                        let loc_cog_vid_local_colormod reg_cog_vid_discrete
                        if (neq32 (and32 reg_cog_vid_discrete 0I8) 0I0):
                            true:
                                let loc_cog_vid_local_colorphs (neq32 (and32 (add32 (and32 (shr32 reg_cog_vid_discrete 0I4) 0If) reg_cog_vid_phase) 0I8) 0I0)
                                let loc_cog_vid_local_colormod (add32 loc_cog_vid_local_colormod (mux32 loc_cog_vid_local_colorphs 0I7 0I1))
                        let reg_cog_vid_cnt0 (and32 (mux32 loc_cog_vid_local_new_set reg_cog_vid_vscl_pixelclocks (mux32 loc_cog_vid_local_new_cnt reg_cog_vid_cnts (sub32 reg_cog_vid_cnt0 0I1))) 0Iff)
                        let reg_cog_vid_setr (and32 (mux32 loc_cog_vid_local_new_set reg_cog_vid_vscl_frameclocks (sub32 reg_cog_vid_setr 0I1)) 0Ifff)
                        if loc_cog_vid_local_new_set:
                            true:
                                let reg_cog_vid_cnts (and32 reg_cog_vid_vscl_pixelclocks 0Iff)
                        let reg_cog_vid_phase (and32 (add32 reg_cog_vid_phase 0I1) 0If)
                        let reg_cog_vid_baseband (add32 (mux32 loc_cog_vid_local_colorphs 0I8 0I0) (and32 (mux32 reg_cog_vid_vcfg_chroma0 loc_cog_vid_local_colormod reg_cog_vid_discrete) 0I7))
                        let reg_cog_vid_composite (and32 (mux32 reg_cog_vid_vcfg_chroma1 loc_cog_vid_local_colormod reg_cog_vid_discrete) 0I7)
                        if (andB reg_cog_vid_vcfg_cmode (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I3)):
                            true:
                                let reg_cog_vid_discrete (and32 (shr32 reg_cog_vid_saved_colors 0I18) 0Iff)
                            false:
                                if (andB reg_cog_vid_vcfg_cmode (eq32 (and32 reg_cog_vid_saved_pixels 0I3) 0I2)):
                                    true:
                                        let reg_cog_vid_discrete (and32 (shr32 reg_cog_vid_saved_colors 0I10) 0Iff)
                                    false:
                                        if (eq32 (and32 reg_cog_vid_saved_pixels 0I1) 0I1):
                                            true:
                                                let reg_cog_vid_discrete (and32 (shr32 reg_cog_vid_saved_colors 0I8) 0Iff)
                                            false:
                                                let reg_cog_vid_discrete (and32 reg_cog_vid_saved_colors 0Iff)
                        if loc_cog_vid_local_new_set:
                            true:
                                let reg_cog_vid_saved_pixels in_cog_vid_pixel
                                let reg_cog_vid_saved_colors in_cog_vid_color
                            false:
                                if loc_cog_vid_local_new_cnt:
                                    true:
                                        let reg_cog_vid_saved_pixels (mux32 reg_cog_vid_vcfg_cmode (or32 (and32 reg_cog_vid_saved_pixels 0Ic0000000) (shr32 reg_cog_vid_saved_pixels 0I2)) (or32 (and32 reg_cog_vid_saved_pixels 0I80000000) (shr32 reg_cog_vid_saved_pixels 0I1)))
        if (orB in_cog_vid_posedge_clk_cog in_cog_vid_negedge_ena):
            true:
                if (notB in_cog_vid_ena):
                    true:
                        let reg_cog_vid_vcfg_vmode 0I0
                        let reg_cog_vid_vcfg_cmode false
                        let reg_cog_vid_vcfg_chroma1 false
                        let reg_cog_vid_vcfg_chroma0 false
                        let reg_cog_vid_vcfg_auralsub 0I0
                        let reg_cog_vid_vcfg_vgroup 0I0
                        let reg_cog_vid_vcfg_vpins 0I0
                    false:
                        if in_cog_vid_setvid:
                            true:
                                let reg_cog_vid_vcfg_vmode (and32 (shr32 in_cog_vid_data 0I1d) 0I3)
                                let reg_cog_vid_vcfg_cmode (eq32 (and32 (shr32 in_cog_vid_data 0I1c) 0I1) 0I1)
                                let reg_cog_vid_vcfg_chroma1 (eq32 (and32 (shr32 in_cog_vid_data 0I1b) 0I1) 0I1)
                                let reg_cog_vid_vcfg_chroma0 (eq32 (and32 (shr32 in_cog_vid_data 0I1a) 0I1) 0I1)
                                let reg_cog_vid_vcfg_auralsub (and32 (shr32 in_cog_vid_data 0I17) 0I7)
                                let reg_cog_vid_vcfg_vgroup (shl32 (and32 (shr32 in_cog_vid_data 0I9) 0I3) 0I3)
                                let reg_cog_vid_vcfg_vpins (and32 in_cog_vid_data 0Iff)
        if in_cog_vid_posedge_clk_cog:
            true:
                if in_cog_vid_setscl:
                    true:
                        let reg_cog_vid_vscl_pixelclocks (and32 (shr32 in_cog_vid_data 0Ic) 0Iff)
                        let reg_cog_vid_vscl_frameclocks (and32 in_cog_vid_data 0Ifff)
                if loc_cog_vid_local_enable:
                    true:
                        let reg_cog_vid_snc1 reg_cog_vid_snc0
                        let reg_cog_vid_snc0 reg_cog_vid_capr
        let reg_cog_vid_capr loc_cog_vid_local_capr_next
        let pin_out (and32 (or32 (or32 (or32 outa outp_cog_ctra_pin_out) outp_cog_ctrb_pin_out) outp_cog_vid_pin_out) dira)
        let pin_dir dira
        let in_cog_ram_posedge_clk_cog posedge_clk_cog
        let in_cog_ram_ena (orB (inRange32 state 0I1 0I3) (andB (andB (eq32 state 0I4) cond) (testBit32 i 0I17)))
        let in_cog_ram_w (andB (eq32 state 0I4) outp_cog_alu_wr)
        let in_cog_ram_d outp_cog_alu_r
        let in_cog_ram_a (mux32 (eq32 state 0I3) px (mux32 (eq32 state 0I1) instr_src instr_dst))
        let outp_cog_ram_q reg_cog_ram_q_reg
        if (andB in_cog_ram_posedge_clk_cog in_cog_ram_ena):
            true:
                let reg_cog_ram_q_reg (arrayAccess reg_cog_ram_r in_cog_ram_a)
                if in_cog_ram_w:
                    true:
                        letarr reg_cog_ram_r in_cog_ram_a in_cog_ram_d
        if (orB posedge_clk_cog negedge_nres):
            true:
                if (notB nres):
                    true:
                        let progctr 0I3e00
                    false:
                        if (andB ena_bus ptr_w):
                            true:
                                let progctr ptr_d
        let match_prev match
        if (orB posedge_clk_cog negedge_ena):
            true:
                if (notB ena):
                    true:
                        let running false
                        let p_reg 0I0
                        let flags 0I0
                        let dira 0I0
                        let cancel false
                    false:
                        if (eq32 state 0I4):
                            true:
                                if (eq32 px 0I1ff):
                                    true:
                                        let running true
                                if (notB (andB cond jump_cancel)):
                                    true:
                                        let p_reg (and32 (add32 px 0I1) 0I1ff)
                                if (andB cond (testBit32 i 0I18)):
                                    true:
                                        let flags (mux32 outp_cog_alu_co (or32 flags 0I2) (and32 flags 0I1))
                                if (andB cond (testBit32 i 0I19)):
                                    true:
                                        let flags (mux32 outp_cog_alu_zo (or32 flags 0I1) (and32 flags 0I2))
                                let cancel (orB (andB cond jump_cancel) (eq32 px 0I1ff))
                        if (andB wio (eq32 instr_dst 0I1f6)):
                            true:
                                let dira outp_cog_alu_r
                if posedge_clk_cog:
                    true:
                        if (andB wio (eq32 instr_dst 0I1f4)):
                            true:
                                let outa outp_cog_alu_r
                        if (eq32 state 0I4):
                            true:
                                let instruction_reg outp_cog_ram_q
                        if (eq32 state 0I2):
                            true:
                                let sy_reg outp_cog_ram_q
                        let match (andB (eq32 state 0I5) (neqB (eq32 (and32 instr_opcode 0I3) 0I1) (eq32 (mux32 (testBit32 i 0I1b) cnt (and32 pin_in source)) dest)))
                        if (eq32 state 0I3):
                            true:
                                let source sx
                                let dest outp_cog_ram_q
                if (notB ena):
                    true:
                        let state 0I0
                    false:
                        switch state:
                            case 0I0:
                                let state 0I1
                            case 0I1:
                                let state 0I2
                            case 0I2:
                                let state 0I3
                            case 0I3 0I5:
                                let state (mux32 (andB cond (muxB (eq32 (and32 instr_opcode 0I3c) 0I0) (notB bus_ack) (muxB (orB (eq32 (and32 instr_opcode 0I3e) 0I3c) (eq32 instr_opcode 0I3e)) (notB match_prev) (andB (eq32 instr_opcode 0I3f) (notB outp_cog_vid_ack))))) 0I5 0I4)
                            case 0I4:
                                let state 0I1
function getParity:
    input I value
    output B returnValue
    local I tmppar
    body:
        let tmppar (xor32 value (shr32 value 0I10))
        let tmppar (xor32 tmppar (shr32 tmppar 0I8))
        let tmppar (xor32 tmppar (shr32 tmppar 0I4))
        let tmppar (xor32 tmppar (shr32 tmppar 0I2))
        let tmppar (xor32 tmppar (shr32 tmppar 0I1))
        let returnValue (testBit32 tmppar 0I0)
function extendToU64ShiftSignToUpper:
    input I value
    output L returnValue
    body:
        let returnValue (or64 (shl64 (cast64 (and32 value 0I80000000)) 0I1) (cast64 (and32 value 0I7fffffff)))
function signedAddOrSub:
    input I dV
    input I sV
    input B doSubtraction
    input B addExtraCarry
    output L returnValue
    body:
        let returnValue (add64 (add64 (extendToU64ShiftSignToUpper dV) (extendToU64ShiftSignToUpper (mux32 doSubtraction (invert32 sV) sV))) (cast64 (mux32 (eqB doSubtraction addExtraCarry) 0I80000000 0I80000001)))
function getSignedResult:
    input L value
    output I returnValue
    body:
        let returnValue (or32 (and32 (lower32 (shr64 value 0I1)) 0I80000000) (and32 (lower32 value) 0I7fffffff))
function getSignedCarry:
    input L value
    output B returnValue
    body:
        let returnValue (eqB (testBit64 value 0I21) (testBit64 value 0I1f))
function getSignedZero:
    input L value
    output B returnValue
    body:
        let returnValue (eq32 (getSignedResult value) 0I0)
function unsignedAddOrSub:
    input I dV
    input I sV
    input B doSubtraction
    input B addExtraCarry
    output L returnValue
    body:
        let returnValue (mux64 doSubtraction (sub64 (cast64 dV) (add64 (cast64 sV) (cast64 (mux32 addExtraCarry 0I1 0I0)))) (add64 (cast64 dV) (add64 (cast64 sV) (cast64 (mux32 addExtraCarry 0I1 0I0)))))
function getUnsignedResult:
    input L value
    output I returnValue
    body:
        let returnValue (lower32 value)
function getUnsignedCarry:
    input L value
    output B returnValue
    body:
        let returnValue (testBit64 value 0I20)
function getUnsignedZero:
    input L value
    output B returnValue
    body:
        let returnValue (eq32 (getUnsignedResult value) 0I0)
function andWithZFlag:
    input I sV
    input I dV
    output I returnValue
    body:
        let returnValue (and32 sV dV)
function orWithZFlag:
    input I sV
    input I dV
    output I returnValue
    body:
        let returnValue (or32 sV dV)
function xorWithZFlag:
    input I sV
    input I dV
    output I returnValue
    body:
        let returnValue (xor32 sV dV)
function shlWithZFlag:
    input I value
    input I shiftBy
    output I returnValue
    body:
        let returnValue (shl32 value shiftBy)
function shrWithZFlag:
    input I value
    input I shiftBy
    output I returnValue
    body:
        let returnValue (shr32 value shiftBy)
function negWithZFlag:
    input I value
    output I returnValue
    body:
        let returnValue (sub32 0I0 value)
function getBitOpResult:
    input I value
    output I returnValue
    body:
        let returnValue value
function getBitOpZero:
    input I value
    output B returnValue
    body:
        let returnValue (eq32 value 0I0)
function decrypt:
    input I indata
    output I returnValue
    body:
        let returnValue (or32 (or32 (or32 (or32 (or32 (shl32 (and32 (shr32 indata 0I3) 0I1) 0I1f) (shl32 (and32 (shr32 indata 0I7) 0I1) 0I1e)) (or32 (shl32 (and32 (shr32 indata 0I15) 0I1) 0I1d) (shl32 (and32 (shr32 indata 0Ic) 0I1) 0I1c))) (or32 (or32 (shl32 (and32 (shr32 indata 0I6) 0I1) 0I1b) (shl32 (and32 (shr32 indata 0I13) 0I1) 0I1a)) (or32 (shl32 (and32 (shr32 indata 0I4) 0I1) 0I19) (shl32 (and32 (shr32 indata 0I11) 0I1) 0I18)))) (or32 (or32 (or32 (shl32 (and32 (shr32 indata 0I14) 0I1) 0I17) (shl32 (and32 (shr32 indata 0If) 0I1) 0I16)) (or32 (shl32 (and32 (shr32 indata 0I8) 0I1) 0I15) (shl32 (and32 (shr32 indata 0Ib) 0I1) 0I14))) (or32 (or32 (shl32 (and32 (shr32 indata 0I0) 0I1) 0I13) (shl32 (and32 (shr32 indata 0Ie) 0I1) 0I12)) (or32 (shl32 (and32 (shr32 indata 0I1e) 0I1) 0I11) (shl32 (and32 (shr32 indata 0I1) 0I1) 0I10))))) (or32 (or32 (or32 (or32 (shl32 (and32 (shr32 indata 0I17) 0I1) 0If) (shl32 (and32 (shr32 indata 0I1f) 0I1) 0Ie)) (or32 (shl32 (and32 (shr32 indata 0I10) 0I1) 0Id) (shl32 (and32 (shr32 indata 0I5) 0I1) 0Ic))) (or32 (or32 (shl32 (and32 (shr32 indata 0I9) 0I1) 0Ib) (shl32 (and32 (shr32 indata 0I12) 0I1) 0Ia)) (or32 (shl32 (and32 (shr32 indata 0I19) 0I1) 0I9) (shl32 (and32 (shr32 indata 0I2) 0I1) 0I8)))) (or32 (or32 (or32 (shl32 (and32 (shr32 indata 0I1c) 0I1) 0I7) (shl32 (and32 (shr32 indata 0I16) 0I1) 0I6)) (or32 (shl32 (and32 (shr32 indata 0Id) 0I1) 0I5) (shl32 (and32 (shr32 indata 0I1b) 0I1) 0I4))) (or32 (or32 (shl32 (and32 (shr32 indata 0I1d) 0I1) 0I3) (shl32 (and32 (shr32 indata 0I18) 0I1) 0I2)) (or32 (shl32 (and32 (shr32 indata 0I1a) 0I1) 0I1) (shl32 (and32 (shr32 indata 0Ia) 0I1) 0I0))))))
function hubPreEval:
    useregset hub
    input I bus_sel
    output I bus_q
    output B bus_c
    output I bus_ack
    output I cog_ena
    output I ptr_w
    output I ptr_d
    body:
        let bus_q bus_q_reg
        let bus_c sys_c
        let ptr_d (shr32 dc 0I4)
        let cog_ena cog_ena_reg
        let bus_ack (mux32 ed (or32 (shl32 (and32 bus_sel 0I3) 0I6) (shr32 bus_sel 0I2)) 0I0)
        let bus_sel_saved bus_sel
        let enc (mux32 (testBit32 ac 0I2) lock_e cog_e)
        let num (mux32 (orB (andB (eq32 (and32 ac 0I7) 0I2) (testBit32 dc 0I3)) (eq32 (and32 ac 0I7) 0I4)) (mux32 (eq32 (and32 enc 0I7f) 0I7f) 0I7 (mux32 (eq32 (and32 enc 0I7f) 0I3f) 0I6 (mux32 (eq32 (and32 enc 0I3f) 0I1f) 0I5 (mux32 (eq32 (and32 enc 0I1f) 0If) 0I4 (mux32 (eq32 (and32 enc 0If) 0I7) 0I3 (mux32 (eq32 (and32 enc 0I7) 0I3) 0I2 (mux32 (eq32 (and32 enc 0I3) 0I1) 0I1 0I0))))))) (and32 dc 0I7))
        let num_dcd (shl32 0I1 num)
        let sys (andB ec (eq32 sc 0I3))
        let cog_start (and32 (mux32 (andB (andB sys (eq32 (and32 ac 0I7) 0I2)) (notB (andB (testBit32 dc 0I3) (eq32 enc 0Iff)))) 0Iff 0I0) num_dcd)
        let ptr_w cog_start
function hubEvalMain:
    useregset hub
    input B ena_bus
    input B nres
    input B bus_r
    input B bus_e
    input B bus_w
    input I bus_s
    input I bus_a
    input I bus_d
    input B posedge_clk_cog
    input B negedge_nres
    output I cfg
    local I ramq
    local I ac0_num_dcd
    local I hb_din
    local I hb_wb
    local B in_hub_mem_posedge_clk_cog
    local B in_hub_mem_ena_bus
    local B in_hub_mem_w
    local I in_hub_mem_wb
    local I in_hub_mem_a
    local I in_hub_mem_d
    local I loc_hub_mem_amasked
    local I loc_hub_mem_newmask
    local I outp_hub_mem_q
    body:
        let cfg cfg_reg
        let hb_wb 0If
        let hb_din dc
        if (eq32 (and32 sc 0I3) 0I1):
            true:
                let hb_din (and32 dc 0Iffff)
                let hb_din (or32 hb_din (shl32 hb_din 0I10))
                let hb_wb (mux32 (testBit32 ac 0I1) 0Ic 0I3)
            false:
                if (eq32 (and32 sc 0I3) 0I0):
                    true:
                        let hb_din (and32 dc 0Iff)
                        let hb_din (or32 hb_din (shl32 hb_din 0I8))
                        let hb_din (or32 hb_din (shl32 hb_din 0I10))
                        let hb_wb (shl32 0I1 (and32 ac 0I3))
        let in_hub_mem_posedge_clk_cog posedge_clk_cog
        let in_hub_mem_ena_bus ena_bus
        let in_hub_mem_w (andB ec (andB wc (neq32 sc 0I3)))
        let in_hub_mem_wb hb_wb
        let in_hub_mem_a (shr32 ac 0I2)
        let in_hub_mem_d hb_din
        let outp_hub_mem_q reg_hub_mem_q_reg
        if (andB in_hub_mem_posedge_clk_cog in_hub_mem_ena_bus):
            true:
                let loc_hub_mem_amasked (and32 in_hub_mem_a 0I3ffff)
                if (andB in_hub_mem_w (notB (testBit32 loc_hub_mem_amasked 0Id))):
                    true:
                        let loc_hub_mem_newmask (or32 (or32 (mux32 (testBit32 in_hub_mem_wb 0I0) 0Iff 0I0) (mux32 (testBit32 in_hub_mem_wb 0I1) 0Iff00 0I0)) (or32 (mux32 (testBit32 in_hub_mem_wb 0I2) 0Iff0000 0I0) (mux32 (testBit32 in_hub_mem_wb 0I3) 0Iff000000 0I0)))
                        letarr reg_hub_mem_memory loc_hub_mem_amasked (or32 (and32 in_hub_mem_d loc_hub_mem_newmask) (and32 (arrayAccess reg_hub_mem_memory loc_hub_mem_amasked) (invert32 loc_hub_mem_newmask)))
                let reg_hub_mem_q_reg (arrayAccess reg_hub_mem_memory loc_hub_mem_amasked)
        if negedge_nres:
            true:
                let ec false
                let ed false
                let cfg_reg 0I0
                let cog_e 0I1
                let lock_e 0I0
                let cog_ena_reg 0I0
        if posedge_clk_cog:
            true:
                let ac0_num_dcd (and32 (mux32 (testBit32 ac 0I0) 0I0 0Iff) num_dcd)
                if (notB nres):
                    true:
                        let ec false
                        let ed false
                        let cfg_reg 0I0
                        let cog_e 0I1
                        let lock_e 0I0
                        let cog_ena_reg 0I0
                    false:
                        if ena_bus:
                            true:
                                let ed ec
                                let ec bus_e
                                let cog_ena_reg (and32 cog_e (invert32 cog_start))
                                if sys:
                                    true:
                                        if (eq32 (and32 ac 0I7) 0I0):
                                            true:
                                                let cfg_reg (and32 dc 0Iff)
                                        if (eq32 (and32 ac 0I6) 0I2):
                                            true:
                                                let cog_e (or32 (and32 cog_e (invert32 num_dcd)) ac0_num_dcd)
                                        if (eq32 (and32 ac 0I6) 0I4):
                                            true:
                                                let lock_e (or32 (and32 lock_e (invert32 num_dcd)) ac0_num_dcd)
                let ramq (mux32 (notB rd) outp_hub_mem_q (decrypt outp_hub_mem_q))
                switch (and32 sd 0I3):
                    case 0I0:
                        let bus_q_reg (and32 (shr32 ramq (shl32 (and32 ad 0I3) 0I3)) 0Iff)
                    case 0I1:
                        let bus_q_reg (and32 (shr32 ramq (shl32 (and32 ad 0I2) 0I3)) 0Iffff)
                    case 0I2:
                        let bus_q_reg ramq
                    case 0I3:
                        let bus_q_reg sys_q
                if ena_bus:
                    true:
                        let rd (andB (notB rc) (testBit32 ac 0If))
                        let rc bus_r
                        let wc bus_w
                        let sd sc
                        let sc bus_s
                        let ad (and32 ac 0I3)
                        if sys:
                            true:
                                if (eq32 (and32 ac 0I6) 0I6):
                                    true:
                                        let sys_q num
                                        let sys_c (testBit32 (shr32 lock_state (and32 dc 0I7)) 0I0)
                                        let lock_state (or32 (and32 lock_state (invert32 num_dcd)) ac0_num_dcd)
                                    false:
                                        if (eq32 (and32 ac 0I7) 0I1):
                                            true:
                                                let sys_q 0I0
                                                if (neq32 (and32 bus_sel_saved 0Ie1) 0I0):
                                                    true:
                                                        let sys_q 0I4
                                                if (neq32 (and32 bus_sel_saved 0I99) 0I0):
                                                    true:
                                                        let sys_q (or32 sys_q 0I2)
                                                if (neq32 (and32 bus_sel_saved 0I55) 0I0):
                                                    true:
                                                        let sys_q (or32 sys_q 0I1)
                                            false:
                                                let sys_q num
                                        let sys_c (eq32 enc 0Iff)
                        let dc bus_d
                        let ac bus_a
